module clk_divider(clk_50M, clk_out);
input clk_50M;  // FPGA clk signal (50MHz)
output clk_out; // clock output (190Hz)

// internal registers 
reg [23:0] clk_div=0;


/* clock divider outputs
[i]  frequency (Hz)  period (s)
     50,000,000.00    0.00002
 0   25,000,000.00    0.00004
 1   12,500,000.00    0.00008
 2    6,250,000.00    0.00016
 3    3,125,000.00    0.00032
 4    1,562,500.00    0.00064
 5      781,250.00    0.00128
 6      390,625.00    0.00256
 7      195,312.50    0.00512
 8       97,656.25    0.01024
 9       48,828.13    0.02048
10       24,414.06    0.04096
11       12,207.03    0.08192
12        6,103.52    0.16384
13        3,051.76    0.32768
14        1,525.88    0.65536
15          762.94    1.31072
16          381.47    2.62144
17          190.73    5.24288
18           95.37   10.48576
19           47.68   20.97152
20           23.84   41.94304
21           11.92   83.88608
22            5.96  167.77216 
23            2.98  335.54432
*/

// frequency divider counter
always@(posedge clk_50M) begin
   clk_div <= clk_div + 1'b1;
end

// selecting the 190Hz output
assign clk_out = clk_div[23];



endmodule
